This invention relates to logic simulators. Such simulators are used, for example, for simulating the operation of complex digital electronic systems, so as to allow the design of the system to be tested and verified without the necessity for constructing an actual hardware prototype of the system.
One known form of logic simulator is described in "Exclusive Simulation of activity in digital networks" by E. G. Ulrich, Communication of the ACM, February 1969, page 102.
The above paper describes a simulator in which operation of the simulated system is represented as a sequence of events. An event may consist, for example, of a transition in the level of a logic signal. The simulator includes a time loop comprising L time slots. Each slot contains a pointer, which points to a list of events that are scheduled to occur at the time corresponding to this time slot. Specifically, an event with event time T is linked to the list for time slot T MOD L (i.e. the remainder after dividing T by L).
In operation, the slots are scanned cyclically to simulate the passage of time. As each slot is scanned, the events in the associated list are processed by calculating their effects on the simulated system. This will, in general, cause further events to be created: for example, a change in state at the input of a logic gate may cause a change in state at the output of the gate after a specified time delay. Whenever a new event is created, it is linked to the event list of the appropriate time slot, so that it will be processed at the correct simulated time.
The above paper teaches that the maximum element delay for the simulated system should normally not exceed the loop length L, so that, at any given time, all the events on the loop must relate to the same cycle around the loop. A consequence of this is that, if the simulated system includes elements with a wide range of delay times, it will be necessary to provide a very large loop. i.e. to make L very large. However, a large loop can degrade the preformance of the simulator.
One way of avoiding large loops, suggested by the above paper, is to use a special extension list, or a second loop, linked to the first slot of the loop, for temporarily holding events whose delay time is greater than the loop length. However, this introduces extra complexity, and slows down the simulation since extra time is required to transfer the contents of the extension list to the main loop.
One object of the present invention is to provide a way of avoiding large loop sizes, without using such an extension list or extra loop.